Reconfigurable arithmetic for HPC

An often overlooked way to increase the efficiency of HPC on FPGA is to tailor, as tightly as possible, the arithmetic to the application. An ideally efficient implementation would, for each of its operations, toggle and transmit just the number of bits required by the application at this point. Conventional microprocessors, with their word-level granularity and fixed memory hierarchy, keep us away from this ideal. FPGAs, with their bit-level granularity, have the potential to get much closer. Therefore, reconfigurable computing should systematically investigate, in an application-specific way, non-standard precisions, but also non-standard number systems and non-standard arithmetic operations. The purpose of this chapter is to review these opportunities. After a brief overview of computer arithmetic and the relevant features of current FPGAs in Section 2, we first discuss in Section 3 the issues of precision analysis (what is the precision required for each computation point?) and arithmetic efficiency (do I need to compute this bit?) in the FPGA context. We then review several approaches to application-specific operator design: operator specialization in Section 4, operator fusion in Section 5, and exotic, non-standard operators in Section 6. Section 7 discusses the application-specific performance tuning of all these operators. Finally, Section 8 concludes by listing the open issues and challenges in reconfigurable arithmetic. The systematic study of FPGA-specific arithmetic is also the object of the FloPoCo project (http://flopoco.gforge.inria.fr/). FloPoCo offers open-source implementations of most of the FPGA-specific operators presented in this chapter, and